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SPT574
FAST, COMPLETE 12-BIT P COMPATIBLE A/D CONVERTER WITH SAMPLE/HOLD
FEATURES
* Improved Version of the HADC574Z * Complete 12-Bit A/D Converter with Sample/Hold, Reference and Clock * Low Power Dissipation (100 mW Max) * 12-Bit Linearity (Over Temp) * 25 s Max Conversion Time * Single +5 V Supply * Full Bipolar and Unipolar Input Range
APPLICATIONS
* * * * * Data Acquisition Systems 8 or 12-Bit P Input Functions Process Control Systems Test and Scientific Instruments Personal Computer Interface
GENERAL DESCRIPTION
The SPT574 is a complete, 12-bit successive approximation A/D converter manufactured in CMOS technology. The device is an improved version of the HADC574Z. Included on chip are an internal reference, clock, and a sample-and-hold. The S/H is an additional feature not available on similar devices. The SPT574 features 25 s (max) conversion time of 10 or 20 V input signals. Also, a three-state output buffer is added for direct interface to an 8, 12, or 16-bit P bus.
The SPT574 has standard bipolar and unipolar input ranges of 10 V and 20 V that are controlled by a bipolar offset pin and laser trimmed for specified linearity, gain and offset accuracy. The power supply is +5 V. The device also has an optional mode control voltage which may be used depending on the application. With a maximum dissipation of 100 mW at the specified voltages, power consumption is about five times lower than that of currently available devices. The SPT574 is available in 28-lead ceramic sidebrazed DIP, PDIP and SOIC packages in the commercial temperature range.
BLOCK DIAGRAM
Nibble A
Output
Nibble B Three-State Buffers And Control
Nibble C
STS
12-Bit SAR
+
Comp Clock
12-Bit Capacitance DAC
Offset/Gain Trim
Control Logic
Ref
20 V In 10 V In BIP Off
12/8
CS
Ao
R/C
CE
Ref Out
AGND
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 C
Supply Voltages Mode Control Voltage (VEE to DGND) .................... 0 to +7 V Logic Supply Voltage (VDD to DGND) ...................0 to +7 V Analog to Digital Ground (AGND to DGND) ................. 1 V Input Voltages Control Input Voltages (to DGND) (CE, CS, Ao, 12/8, R/C) ......................... -0.5 to VDD +0.5 V Analog Input Voltage (to AGND) (REF IN, BIP OFF, 10 VIN) ...................................... 16.5 V 20 V VIN Input Voltage (to AGND) .............................. 24 V Note: Output Reference Output Voltage .............. Indefinite Short to GND Momentary Short to VDD Temperature Operating Temperature, Ambient .................... 0 to +70 C Junction ......................... +165 C Lead Temperature, (Soldering 10 Seconds) ........... +300 C Storage Temperature .................................... -65 to +150 C
Operation at any Absolute Maximum Rating is not implied. See Operating Conditions for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
TEST LEVEL
MIN
SPT574C TYP MAX
MIN
SPT574B TYP MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Resolution Linearity Error Differential Linearity Unipolar Offset; 10 V, 20 V Bipolar Offset; 5 V, 10 V Full Scale Calibration Error1 Full Scale Calibration Error1 Temperature Coefficients Unipolar Offset Bipolar Offset Full Scale Calibration Power Supply Rejection +4.75 V+25 C Adjustable to Zero +25 C Adjustable to Zero +25 C Adjustable to Zero
VI VI VI VI VI VI V V V V Max Change in Full Scale Calibration VI 0.47 1.0 2.0 12 12
12 1 12 2 10 0.3 0.37 1.0 2.0 12 0.5
12 0.5 2 4 0.3
Bits LSB Bits LSB LSB % of FS % of FS ppm/C ppm/C ppm/C
No Adjustment to Zero TA = 0 to +70 C
Using Internal Reference
0.5
LSB
VI VI VI VI VI VI
-5 -10 0 0 15 60 21 84
+5 +10 +10 +20
-5 -10 0 0 15 60 21 84
+5 +10 +10 +20
Volts Volts Volts Volts k k
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ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
TEST LEVEL
MIN
SPT574C TYP MAX
MIN
SPT574B TYP MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Power Supplies Operating Voltage Range VDD VEE2 Operating Current IDD IEE2 Power Dissipation Internal Reference Voltage Output Current3 DIGITAL CHARACTERISTICS Logic Inputs (CE, CS , R/C , Ao, 12/8 ) Logic 0 Logic1 Current Capacitance Logic Outputs (DB11-DB0, STS) Logic 0 Logic 1 Leakage Capacitance AC Accuracy Spurious Free Dyn. Range Total Harmonic Distortion Signal-to-Noise Ratio Signal-to-Noise & Distortion (SINAD) Intermodulation Distortion fS=40 kHz, fIN=10 kHz V V V V 78 -77 72 71 78 -77 72 71 dB dB dB dB VI VI VI V -0.5 2.0 -5.0 0. 1 5 +0.8 5.5 5.0 -0.5 2.0 -5.0 0. 1 5 +0.8 5.5 5.0 Volts Volts A pF
IV IV IV IV VI VI VI
+4.5
+5.5 VDD 13 167 65 20 100 2.6
+4.5
+5.5 VDD 13 167 65 20 100 2.6
Volts Volts mA A mW Volts mA
VEE = +5 V
2.4 0.5
2.5
2.4 0.5
2.5
(ISink = 1.6 mA) (ISOURCE = 500 A) (High Z State, DB11-DB0 Only)
VI VI VI V
+0.4 +2.4 -5 0.1 5 +5 +2.4 -5 0.1 5
+0.4 +5
Volts Volts A pF
fIN=10 kHz; V -75 -75 dB fIN2=11.5 kHz Note 1: Fixed 50 resistor from REF OUT to REF IN and REF OUT to BIP OFF. Note 2: VEE is optional and is only used to set the mode for the internal sample/hold. When not using VEE, the pin should be treated as a no connect. If VEE is connected to 0 to -15 V, aperture delay (tAP) will increase from 20 ns (typ) to 4000 ns (typ). Note 3: Available for external loads; external load should not change during conversion.
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ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
TEST LEVEL
MIN
SPT574C TYP MAX
MIN
SPT574B TYP MAX
UNITS
AC ELECTRICAL CHARACTERISTICS4
Convert Mode Timing tDSC STS Delay from CE tHEC CE Pulse Width tSSC CS to CE Setup tHSC CS Low during CE High tSRC R/C to CE Setup tHRC R/C Low During CE High tSAC Ao to CE Setup tHAC Ao Valid During CE High tC Conversion Time5 12-Bit Cycle 8-Bit Cycle Read Mode Timing tDD Access Time from CE tHD Data Valid After CE Low tHL Output Float Delay tSSR CS to CE Setup tSRR R/C to CE Setup tSAR Ao to CE Setup tHSR CS Valid After CE Low tHRR R/C High After CE Low tHS STS Delay After Data Valid tHAR Ao Valid after CE Low VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI 60 30 20 20 0 20 20 22 16 75 35 100 0 25 25 18 150 25 150 50 0 50 0 1000 0 300 50 200 50 50 50 50 50 0 50 60 30 20 20 0 20 20 22 16 75 35 100 0 25 25 18 150 150 200 ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns 1000 ns ns ns
50 50 50 50 50 0 50
25 50 0 50 0 0 300 50
400
400
Note 4: Time is measured from 50% level of digital transitions. Note 5: Includes acquisition time.
Figure 1 - Convert Mode Timing Diagram
Figure 2 - Read Mode Timing Diagram
CE
CE CS
t SSC
t HEC
CS
t SSR
t HSR
t HRR
t SRC
R/C
t HSC
R/C
t SRR
t HRC
Ao
Ao
t SAC
STS
t SAR
t HAR
t HAC
STS
t DSC
tC
t HS
HIGH DB11-DB0 IMPEDANCE DATA VALID
t HD
DB11-DB0
High Impedance
t DD
t HL
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ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
TEST LEVEL
MIN
SPT574C TYP MAX
MIN
SPT574B TYP MAX
UNITS
AC ELECTRICAL CHARACTERISTICS4
Stand-Alone Mode Timing tHRL Low R/C Pulse Width tDS STS Delay from R/C tHDR Data Valid After R/C Low tHS STS Delay After Data Valid tHRH High R/C Pulse Width tDDR Data Access Time Sample-and-Hold Aperture Delay Aperture Uncertainty Time VI VI VI VI VI VI VEE = +5 V VEE = +5 V IV V 25 300 100 400 25 200 1000 150 20 300 20 300 25 300 100 400 25 200 1000 150 ns ns ns ns ns ns ns ps, RMS
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range.
Figure 3 - Low Pulse for R/C - Outputs Enabled After Conversion
t R/C HRL
Figure 4 - High Pulse for R/C - Outputs Enabled While R/C is High, Otherwise High Impedance
R/C
t
HRH
t
DS
t
DS
STS t t t C
STS t
t HDR
C t HS
DB11-DB0 HIGH-Z
DDR
HDR
HIGH-Z DATA VALID
DB11-DB0
DATA VALID
DATA VALID
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CIRCUIT OPERATION
The SPT574 is a complete 12-bit analog-to-digital converter that consists of a single chip version of the industry standard 574. This single chip contains a precision 12-bit capacitor digital-to-analog converter (CDAC) with voltage reference, comparator, successive approximation register (SAR), sampleand-hold, clock, output buffers and control circuitry to make it possible to use the SPT574 with few external components. When the control section of the SPT574 initiates a conversion command, the clock is enabled and the successive-approximation register is reset to all zeros. Once the conversion cycle begins, it cannot be stopped or restarted and data is not available from the output buffers. The SAR, timed by the clock, sequences through the conversion cycle and returns an end-of-convert flag to the control section of the ADC. The clock is then disabled by the control section, the output status goes low, and the control section is enabled to allow the data to be read by external command. The internal SPT574 12-bit CDAC is sequenced by the SAR starting from the MSB to the LSB at the beginning of the conversion cycle to provide an output voltage from the CDAC that is equal to the input signal voltage (which is divided by the input voltage divider network). The comparator determines whether the addition of each successively-weighted bit voltage causes the CDAC output voltage summation to be greater or less than the input voltage; if the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12-bit binary code which accurately represents the input signal to within 1/2 LSB. The internal reference provides the voltage reference to the CDAC with excellent stability over temperature and time. The reference is trimmed to 2.5 volts and can supply at least 0.5 mA to an external load. Any external load on the SPT574 reference must remain constant during conversion. The sample-and-hold feature is a bonus of the CDAC architecture. Therefore the majority of the S/H specifications are included within the A/D specifications. Although the sample-and-hold circuit is not implemented in the classical sense, the sampling nature of the capacitive DAC makes the SPT574 appear to have a built-in sampleand-hold. This sample-and-hold action substantially increases the signal bandwidth of the SPT574 over that of similar competing devices. Note that even though the user may use an external sampleand-hold for very high frequency inputs, the internal sampleand-hold still provides a very useful isolation function. Once the internal sample is taken by the CDAC capacitance, the input of the SPT574 is disconnected from the user's sampleand-hold. This prevents transients occurring during conversion from affecting the attached sample-and-hold buffer. All
other 574 circuits will cause a transient load current on the sample-and-hold which will upset the buffer output and may add error to the conversion itself. Furthermore, the isolation of the input after the acquisition time in the SPT574 allows the user an opportunity to release the hold on an external sample-and-hold and start it tracking the next sample. This increases system throughput with the user's existing components.
TYPICAL INTERFACE CIRCUIT
The SPT574 is a complete A/D converter that is fully operational when powered up and issued a Start Convert Signal. Only a few external components are necessary as shown in figures 5 and 6. The two typical interface circuits are for operating the SPT574 in either an unipolar or bipolar input mode. Information on these connections and on conditions concerning board layout to achieve the best operation are discussed below. For each application of this device, strict attention must be given to power supply decoupling, board layout (to reduce pickup between analog and digital sections), and grounding. Digital timing, calibration and the analog signal source must be considered for correct operation.
POWER SUPPLIES
The supply voltage for the SPT574 must be kept as quiet as possible from noise pickup and also regulated from transients or drops. Because the part has 12-bit accuracy, voltage spikes on the supply lines can cause several LSB deviations on the output. Switching power supply noise can be a problem. Careful filtering and shielding should be employed to prevent the noise from being picked up by the converter. VDD should be bypassed with a 10 F tantalum capacitor located close to the converter to filter noise and counter the problems caused by the variations in supply current. VEE is only used as a logic input and is immune to typical supply variation.
GROUNDING CONSIDERATIONS
Resistance of any path between the analog and digital grounds should be as low as possible to accommodate the ground currents present with this device. To achieve specified accuracy, a double-sided printed circuit board with a copper ground plane on the component side is recommended. Keep analog signal traces away from digital lines. It is best to lay the PC board out such that there is an analog section and a digital section with a single point ground connection between the two through an RF bead located as close to the device as possible. If possible, run analog signals between ground traces and cross digital lines at right angles only.
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The analog and digital common pins should be tied together as close to the package as possible to guarantee best performance. The code dependent currents flow through the VDD terminal and not through the analog and digital common pins.
RANGE CONSIDERATIONS
The SPT574 may be operated by a microprocessor or in the stand-alone mode. The part has four standard input ranges: 0 V to +10 V, 0 V to +20 V, 5 V and 10 V. The maximum errors that are listed in the specifications for gain and offset may be adjusted externally to zero as explained in the next two sections.
The gain adjustment should be done at positive full scale. The ideal input corresponding to the last code change is applied. This is 1 and 1/2 LSB below the nominal full scale which is +9.9963 V for the 10 V range and +19.9927 V for the 20 V range. Adjust the gain potentiometer R2 for flicker between codes 1111 1111 1110 and 1111 1111 1111. If calibration is not necessary for the intended application, replace R2 with a 50 , 1% metal film resistor and remove the network from the BIP OFF pin. Connect the BIP OFF pin to AGND. Connect the analog input to the 10 V IN pin for the 0 to 10 V range or to the 20 V IN pin for the 0 to 20 V range. BIPOLAR The gain and offset errors listed in the specification may be adjusted to zero using the potentiometers R1 and R2. (See figure 6.) If adjustment is not needed, either or both pots may be replaced by a 50 , 1% metal film resistor. To calibrate, connect the analog input signal to the 10 V IN pin for a 5 V range or to the 20 V IN pin for a 10 V range. First apply a DC input voltage 1/2 LSB above negative full scale which is -4.9988 V for the 5 V range or -9.9976 V for the 10 V range. Adjust the offset potentiometer R1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001. Next, apply a DC input voltage 1 and 1/2 LSB below positive full scale which is +4.9963 V for the 5 V range or +9.9927 V for the 10 V range. Adjust the gain potentiometer R2 for flicker between codes 1111 1111 1110 and 1111 1111 1111.
CALIBRATION & CONNECTION PROCEDURES
UNIPOLAR The calibration procedure consists of adjusting the converter's most negative output to its ideal value for offset adjustment and then adjusting the most positive output to its ideal value for gain adjustment. Starting with offset adjustment and referring to figure 5, the midpoint of the first LSB increment should be positioned at the origin to get an output code of all 0s. To do this, an input of +1/2 LSB or +1.22 mV for the 10 V range and +2.44 mV for the 20 V range should be applied to the SPT574. Adjust the offset potentiometer R1 for code transition flickers between 0000 0000 0000 and 0000 0000 0001. Figure 5 - Unipolar Input Connections
Figure 6 - Bipolar Input Connections
Output Bits
Output Bits
R/C CS Ao 12/8 CE Control Logic Nibble A Nibble B Nibble C
R/C CS Ao 12/8
12-Bits Oscillator 12-Bit SAR STS
Nibble A Control Logic
Nibble B
Nibble C
Three-State Buffers And Control
Three-State Buffers And Control
CE
12-Bits Oscillator 12-Bit SAR STS VDD Strobe 12-Bits DGND .1 F +5 V
R1 100 k -15 V +15 V 12-Bits
VDD Strobe .1 F DGND 0 to 10 V 10 V In 20 V In BIP Off Sample/Hold
MSB
+5 V
CDAC
LSB
Comp
5 V Analog Inputs 10 V 100 R1
10 V In 20 V In BIP Off
Sample/Hold
MSB
CDAC
LSB
Comp
100 k
Analog Inputs 0 to 20 V
100
VRef Out
Ref Amp
Ref
Offset/Gain Trim Network
VRef Out
Ref Amp
Ref
Offset/Gain Trim Network
100 (Calibration)
R2
VRef In
100 R1
VRef In
VEE
VEE
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ALTERNATIVE In some applications, a full scale of 10.24 V (for an LSB of 2.5 mV) or 20.48 V (for an LSB of 5.0 mV) is more convenient. In the unipolar mode of operation, replace R2 with a 200 potentiometer and add 150 in series with the 10 V IN pin for 10.24 V input range or 500 in series with the 20 V IN pin for 20.48 V input range. In bipolar mode of operation, replace R1 with a 500 potentiometer (in addition to the previous changes). The calibration will remain similar to the standard calibration procedure.
Figure 7 - Interfacing the SPT574 to an 8-Bit Data Bus
Ao
Address Bus
~
STS 12/8 MSB
Ao
Data Bus
CONTROLLING THE SPT574
The SPT574 can be operated by most microprocessor systems due to the control input pins and on-chip logic. It may also be operated in the stand-alone mode and enabled by the R/C input pin. Full P control consists of selecting an 8 or 12-bit conversion cycle, initiating the conversion, and reading the output data when ready. The output read has the options of choosing either 12-bits at once or 8 bits followed by 4-bits in a left-justified format. All five control inputs are TTL/ CMOS compatible and include 12/8 , CS , Ao, R/C and CE. The use of these inputs in controlling the converter's operations is shown in table I, and the internal control logic is shown in a simplified schematic in figure 10. STAND-ALONE OPERATION The simplest interface is a control line connected to R/C . The output controls must be tied to known states as follows: CE and 12/8 are wired high, Ao and CS are wired low. The output data arrives in words of 12-bits each. The limits on R/C duty cycle are shown in figures 3 and 4. It may have a duty cycle within and including the extremes shown in the specifications. In general, data may be read when R/C is high unless STS is also high, indicating a conversion is in progress. Table I - Truth Table for the SPT574 Control Inputs
CE 0 X CS X 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 R/C X X 0 0 0 0 12/8 X X X X X X X X 1 0 0 Ao X X 0 1 0 1 0 1 X 0 1 Operation None None Initiate 12 bit conversion Initiate 8 bit conversion Initiate 12 bit conversion Initiate 8 bit conversion Initiate 12 bit conversion Initiate 8 bit conversion Enable 12 bit Output Enable 8 MSB's Only Enable 4 LSB's Plus 4 Trailing Zeroes
LSB DIG COM
CONTROLLED OPERATION
CONVERSION LENGTH A conversion start transition latches the state of Ao as shown in figure 7 and table I. The latched state determines if the conversion stops with 8 bits (Ao high) or continues for 12 bits (Ao low). If all 12 bits are read following an 8-bit conversion, the three LSBs will be a logic 0 and DB3 will be a logic 1. Ao is latched because it is also involved in enabling the output buffers as will be explained later. No other control inputs are latched. CONVERSION START A conversion may be initiated by a logic transition on any of the three inputs: CE, CS , R/C , as shown in table I. The last of the three to reach the correct state starts the conversions, so one, two or all three may be dynamically controlled. The nominal delay from each is the same and all three may change state simultaneously. In order to assure that a particular input controls the start of conversion, the other two should be set up at least 50 ns earlier. Refer to the convert mode timing specifications. The Convert Start timing diagram is illustrated in figure 1. The output signal STS is the status flag and goes high only when a conversion is in progress. While STS is high, the output buffers remain in a high impedance state so that data can not be read. Also, when STS is high, an additional Start Convert will not reset the converter or reinitiate a conversion. Note, if Ao changes state after a conversion begins, an additional Start Convert command will latch the new start of Ao and possibly cause a wrong cycle length for that conversion (8 versus 12 bits).
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READING THE OUTPUT DATA The output data buffers remain in a high impedance state until the following four conditions are met: R/C is high, STS is low, CE is high, and CS is low. The data lines become active in response to the four conditions and output data according to the conditions of 12/8 and Ao. The timing diagram for this process is shown in figure 2. When 12/8 is high, all 12 data outputs become active simultaneously and the Ao input is ignored. This is for easy interface to a 12 or 16-bit data bus. The 12/8 input is usually tied high or low, although it is TTL/CMOS compatible. When 12/8 is low, the output is separated into two 8-bit bytes as shown below. Figure 8 - Output When 12/8 Is Low
SAMPLE-AND-HOLD (S/H) CONTROL MODE This control mode is provided to allow full use of the internal S/H, eliminating the need for an external S/H in most applications. The SPT574 in the control mode also eliminates the need for one of the control signals, usually the convert command. The command that puts the internal S/H in the hold state also initiates a conversion, reducing time constraints in many systems. As soon as the conversion is completed the internal S/H immediately begins slewing to track the input signal. See figure 9. In the control mode it is assumed that during the required 4 s acquisition time the signal is not slewing faster than the slew rate of the SPT574. No assumption is made about the input level after the convert command arrives since the input signal is sampled and conversion begins immediately after the convert command. This means that the convert command can be used to switch an input multiplexer or change gains on a programmable gain amplifier, allowing the input signal to settle before the next acquisition at the end of the conversion. Because aperture jitter is minimized by the internal S/H, a high input frequency can be converted without an external S/H. See table II. Table II - Conversion Timing (VEE = +5 V) S/H Control Mode Min Typ Max 22 16 18 12 4 20 0.3 25 18
BYTE 1 XXXX MSB XXXX
BYTE 2 XXXX LSB OOOO
This configuration makes it easy to connect to an 8-bit data bus as shown in figure 7. The Ao control can be connected to the least significant bit of the address bus in order to store the output data into two consecutive memory locations. When Ao is pulled low, the 8 MSBs are enabled only. When Ao is high, the 4 MSBs are disabled, bits 4 through 7 are forced to a zero and the four LSBs are enabled. The two byte format is left justified data as shown above and can be considered to have a decimal point or binary to the left of byte 1. Ao may be toggled without damage to the converter at any time. Break-before-make action is guaranteed between the two data bytes. This assures that the outputs in figure 7 will never be enabled at the same time. In figure 2, it can be seen that a read operation usually begins after the conversion is completed and STS is low. If earlier access is needed, the read can begin no later than the addition of time tDD and tHS before STS goes low. Figure 9 - S/H Control Mode Timing (VEE = +5 V)
Parameter Throughput Time (tAQ+tC) 12-Bit Conversions 8-Bit Conversions Conversion Time (tC) 12-Bit Conversions 8-Bit Conversions Acquisition Time(tAC) Aperture Delay (tAP) Aperture Uncertainty (tJ)
Units s s s s s ns ns
R/C tAP
Signal Acquisition
tC
Conversion Signal Acquisition
tAQ
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Figure 10 - Control Logic
Nibble B Zero Override Nibble A,B
Input Buffers 12/8 Nibble C
CS
Read Control
A
R/C H CE D CK R EOC8 CK Q D Q AO Latch EOC12 Q
Delay
STS
PACKAGE OUTLINES
28-Lead PDIP
SYMBOL A B C D E F G H I J K
INCHES MIN MAX 0.115 0.014 0.030 0.008 0.125 0.600 0.485 1.380 0.005 0.250 0.200 0.022 0.100 0.070 0.015 0.195 0.625 0.580 1.565 0.040
MILLIMETERS MIN MAX 2.92 0.36 0.76 0.20 3.18 15.24 12.32 35.05 0.13 6.35 5.08 0.56 2.54 1.78 0.38 4.95 15.88 14.73 39.75 1.02
K
28
I
1
J H A G
B
F
C
D
E
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PACKAGE OUTLINES
28-Lead Sidebrazed
28
H
INCHES SYMBOL A
I
MILLIMETERS MIN 1.96 0.41 2.41 1.02 5.46 35.26 14.86 0.23 15.24 MAX 2.36 0.51 2.67 1.27 typ 1.52 5.97 35.86 15.37 0.30 15.75 0.093 0.020
MIN 0.077 0.016 0.095 0.040 0.215 1.388 0.585 0.009 0.600
MAX
B C D E F G
1 G A E F C B D
J
0.105 .050 typ 0.060 0.235 1.412 0.605 0.012 0.620
H I J
28-Lead SOIC
INCHES SYMBOL A
28
MILLIMETERS MAX 0.712 0.012 .050 typ 0.019 0.012 0.104 0.050 0.419 0.299 MIN 17.68 0.10 0.36 0.23 2.03 0.41 10.01 7.39 MAX 18.08 0.30 1.27 typ 0.48 0.30 2.64 1.27 10.64 7.59
MIN 0.696 0.004 0.014 0.009 0.080 0.016 0.394 0.291
B C
IH
D E F
1
G H I
A F H
B C D E G
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PIN ASSIGNMENTS
1 VDD 2 12/8 3 CS 4 Ao 5 R/C 6 CE 7 N/C 8 REF OUT 9 AGND 10 REF IN 11 VEE 12 BIP OFF 13 10 V IN 14 20 V IN STS DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND 28 27 26 25 24 23 22 21 20 19 18 17
PIN FUNCTIONS
NAME VDD 12/8 FUNCTION Logic Supply Voltage, Nominally +5 V Data Mode Selection Chip Selection Byte Address/Short Cycle Read/Convert Chip Enable Mode Control Voltage, Nominally +5 V Reference Output, Nominally +2.5 V Analog Ground Reference Input Pin Not Connected to Device Bipolar Offset 10 Volt Analog Input 20 Volt Analog Input Digital Ground Digital Data Output DB11 - MSB DB0 - LSB Status
CS
Ao R/C CE VEE REF OUT AGND REF IN N/C BIP OFF
16
10 V IN
15
20 V IN
28-LEAD DIP/SOIC
DGND DB0 - DB11 STS
ORDERING INFORMATION
LINEARITY ERROR MAX 1/2 LSB 1/2 LSB 1/2 LSB 1 LSB 1 LSB 1 LSB PACKAGE TYPE 28L Plastic DIP 28L Sidebrazed DIP 28L SOIC 28L Plastic DIP 28L Sidebrazed DIP 28L SOIC
PART NUMBER SPT574BCN SPT574BCJ SPT574BCS SPT574CCN SPT574CCJ SPT574CCS
TEMPERATURE RANGE 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT
SPT574
12
8/1/00

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